|Publisher||Society of Exploration Geophysicists||Language||English|
|Content Type||Conference Paper|
|Title||An Implementation of the Acoustic Wave Equation On FPGAs|
|Authors||Tamas Nemeth, Joe Stefani, Wei Liu, Chevron; Rob Dimond, Oliver Pell, Maxeler; Ray Ergas, formerly Chevron|
|Source||2008 SEG Annual Meeting, November 9 - 14, 2008 , Las Vegas, Nevada|
|Copyright||2008. Society of Exploration Geophysicists|
We utilize FPGA chips as co-processors in a PCI Express configuration to accelerate an acoustic isotropic modeling application. We have achieved speedups of 2 orders of magnitude when compared to a single-core implementation on modern CPU chips. These results indicate that FPGAbased acceleration technology may become a viable alternative for some tasks in seismic data processing.
High-performance computing (HPC) is at a crossroads since 2004, when the single-core CPU clock frequencies stopped increasing. Since then several alternative technologies became viable for HPC: (a) "mainstream" multi-core CPU servers; (b) stream computing on graphics card (GPU) co-processors; (c) Cell chip configurations; and (d) FPGA chips as co-processors.
Hardware accelerators as co-processors are emerging as a powerful solution to computationally intensive problems. A standard desktop PC or cluster node can be augmented with additional hardware dedicated to providing substantially increased performance for particular applications. Previous efforts have shown that FPGA-based hardware accelerators can offer order-of-magnitude greater performance than conventional CPUs, providing the target algorithm performs a large number of operations per data point. FPGAs are off-the-shelf chips with a configurable "sea" of logic and memory that can be used to implement digital circuits. FPGAs can be attached to the compute system either through the main system bus or as PCI Express cards (or similar) and are typically configured as highly parallel stream processors. FPGA acceleration has been successfully demonstrated in a variety of application domains including computational finance (Zhang et al., 2005), fluid dynamics (Sano et al., 2007), cryptography (Cheung et al., 2005) and seismic processing (Bean and Gray, 1997; He et al., 2005a; He et al., 2005b; Pell and Clapp, 2007).
While these co-processor technologies are still out of the mainstream HPC, they offer potential speedups that cannot be ignored. The potential performance gains have large implications on seismic data processing and therefore it is important to systematically evaluate these technologies. In this study we present acoustic isotropic modeling results using a Maxeler PCI Express x16 acceleration card that is based on FPGA chips. We first describe the considerations related to producing an FPGA implementation and then compare the traces with those from CPU implementations.
Code Analysis and Implementation
The acoustic forward modeling application in consideration is 3D finite difference, with 4th-order in time, 12th order in space and uses single precision floating point arithmetic. Input data consist of two 3D earth model arrays (velocity and density) and a source function. The application iterates for a number of time steps with three wavefield arrays. Total memory requirement on the CPU therefore is to store 4-bytes per point, for 5 arrays, or 20 x N3, where N is a spatial dimension. Since acceleration has the biggest impact for large projects, we assume that any solution should work for model sizes of N=1000, with a total memory of 20 GB or more.
The acoustic variable density modeling code contains a kernel which consumes the majority of the compute cycles, indicating that the algorithm is a good candidate for acceleration. The finite difference operators are calculated to minimize the relative phase velocity error over the bandwidth.
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